Please use this identifier to cite or link to this item: https://hdl.handle.net/11147/2553
Title: Towards test case generation for synthesizable VHDL programs using model checker
Authors: Ayav, Tolga
Tuğlular, Tuğkan
Belli, Fevzi
Ayav, Tolga
Tuğlular, Tuğkan
Keywords: Test case generation
Model checking
VHDL
Program transformation
Timed automata
Issue Date: Jul-2010
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: Ayav, T., Tuğlular, T., and Belli, F. (2010, June 9-11). Towards test case generation for synthesizable VHDL programs using model checker. Paper presneted at the 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion. doi:10.1109/SSIRI-C.2010.22
Abstract: VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study.
Description: 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010
URI: http://doi.org/10.1109/SSIRI-C.2010.22
http://hdl.handle.net/11147/2553
ISBN: 9780769540870
Appears in Collections:Computer Engineering / Bilgisayar Mühendisliği
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection

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