Please use this identifier to cite or link to this item: https://hdl.handle.net/11147/2553
Full metadata record
DC FieldValueLanguage
dc.contributor.authorAyav, Tolga-
dc.contributor.authorTuğlular, Tuğkan-
dc.contributor.authorBelli, Fevzi-
dc.date.accessioned2016-11-30T13:10:53Z-
dc.date.available2016-11-30T13:10:53Z-
dc.date.issued2010-07-
dc.identifier.citationAyav, T., Tuğlular, T., and Belli, F. (2010, June 9-11). Towards test case generation for synthesizable VHDL programs using model checker. Paper presneted at the 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion. doi:10.1109/SSIRI-C.2010.22en_US
dc.identifier.isbn9780769540870-
dc.identifier.urihttp://doi.org/10.1109/SSIRI-C.2010.22-
dc.identifier.urihttp://hdl.handle.net/11147/2553-
dc.description4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010en_US
dc.description.abstractVHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.ispartof4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010en_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectTest case generationen_US
dc.subjectModel checkingen_US
dc.subjectVHDLen_US
dc.subjectProgram transformationen_US
dc.subjectTimed automataen_US
dc.titleTowards test case generation for synthesizable VHDL programs using model checkeren_US
dc.typeConference Objecten_US
dc.authoridTR114453en_US
dc.authoridTR114656en_US
dc.institutionauthorAyav, Tolga-
dc.institutionauthorTuğlular, Tuğkan-
dc.departmentIzmir Institute of Technology. Computer Engineeringen_US
dc.identifier.startpage46en_US
dc.identifier.endpage53en_US
dc.identifier.scopus2-s2.0-77956097952en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.identifier.doi10.1109/SSIRI-C.2010.22-
dc.relation.doi10.1109/SSIRI-C.2010.22en_US
dc.coverage.doi10.1109/SSIRI-C.2010.22en_US
local.message.claim2022-06-03T14:19:15.136+0300|||rp00375|||submit_approve|||dc_contributor_author|||None*
item.openairetypeConference Object-
item.languageiso639-1en-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.grantfulltextopen-
item.fulltextWith Fulltext-
item.cerifentitytypePublications-
crisitem.author.dept03.04. Department of Computer Engineering-
crisitem.author.dept03.04. Department of Computer Engineering-
crisitem.author.dept03.04. Department of Computer Engineering-
Appears in Collections:Computer Engineering / Bilgisayar Mühendisliği
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
Files in This Item:
File Description SizeFormat 
2553.pdfConference Paper406.69 kBAdobe PDFThumbnail
View/Open
Show simple item record

CORE Recommender

SCOPUSTM   
Citations

2
checked on Oct 1, 2022

Page view(s)

106
checked on Oct 3, 2022

Download(s)

110
checked on Oct 3, 2022

Google ScholarTM

Check

Altmetric


Items in GCRIS Repository are protected by copyright, with all rights reserved, unless otherwise indicated.