Please use this identifier to cite or link to this item: https://hdl.handle.net/11147/2548
Title: Model based testing of VHDL programs
Authors: Ayav, Tolga
Tuğlular, Tuğkan
Belli, Fevzi
Keywords: Model based testing
VHDL
Timed automata
Model checking
Engineering controlled terms
Issue Date: Sep-2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: Ayav, T., Tuğlular, T., and Belli, F.(2015, July 1-5). Model based testing of VHDL programs. Paper presented at the 39th IEEE Annual Computer Software and Applications Conference Workshops, COMPSACW 2015. doi:10.1109/COMPSAC.2015.198
Abstract: VHDL programs are often validated by means of test benches constructed from formal system specification. To include real-time properties of VHDL programs, the proposed approach first transforms them to concurrently running network of timed automata and then performs model checking on properties taken from the specification. Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor. As presented, the approach enables testing both hardware and software at once.
Description: 39th IEEE Annual Computer Software and Applications Conference Workshops, COMPSACW 2015; Taichung; Taiwan; 1 July 2015 through 5 July 2015
URI: http://doi.org/10.1109/COMPSAC.2015.198
http://hdl.handle.net/11147/2548
ISBN: 9781467365635
ISSN: 0730-3157
Appears in Collections:Computer Engineering / Bilgisayar Mühendisliği
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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