Transforming Vhdl To Timed Automata

Please use this identifier to cite or link to this item: https://hdl.handle.net/11147/2571

Title:	Transforming Vhdl To Timed Automata
Authors:	Ayav, Tolga Tuğlular, Tuğkan Belli, Fevzi
Keywords:	VHDL Timed automata
Publisher:	Izmir Institute of Technology
Abstract:	This report presents the transformation of behavioral VHDL programs to Timed Automata.
Description:	Technical Report No: IYTE-COMPENG-2015-001
URI:	http://hdl.handle.net/11147/2571
Appears in Collections:	Computer Engineering / Bilgisayar Mühendisliği