Please use this identifier to cite or link to this item: https://hdl.handle.net/11147/2571
Title: Transforming VHDL to timed automata
Authors: Ayav, Tolga
Tuğlular, Tuğkan
Belli, Fevzi
Keywords: VHDL
Timed automata
Issue Date: 2-Dec-2016
Publisher: Izmir Institute of Technology
Abstract: This report presents the transformation of behavioral VHDL programs to Timed Automata.
Description: Technical Report No: IYTE-COMPENG-2015-001
URI: http://hdl.handle.net/11147/2571
Appears in Collections:Computer Engineering / Bilgisayar Mühendisliği

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