Please use this identifier to cite or link to this item: https://hdl.handle.net/11147/2549
Title: Model checker-based delay fault testing of sequential circuits
Authors: Takan, Savaş
Güler, Berkin
Ayav, Tolga
Keywords: Delay fault testing
VLSI
Model checker
Issue Date: May-2015
Publisher: Springer Verlag
Source: Takan, S., Güler, B., and Ayav, T. (2015). Model checker-based delay fault testing of sequential circuits. In J. M. P. Cardoso (Ed.), ARCS 2015 Proceedings. Paper presented at the 28th International Conference on Architecture of Computing Systems, Porto, Portugal, 24-27 March (pp. 1-7). Berlin: VDE.
Abstract: This paper applies model checker-based testing, a well-known method from software engineering, to the delay fault testing of synchronous sequential logic circuits. We first model the circuit as timed automata to reveal its timing characteristics. The model is repeatedly mutated by injecting the delay faults under a certain fault assumption and all the mutant models are checked against the given properties by exploiting a model checker. Counterexamples returned from the model checker form the basis of test input sequences. Finally, the test suite minimization is defined as an integer programming problem.
URI: http://hdl.handle.net/11147/2549
ISBN: 9783800736577
Appears in Collections:Computer Engineering / Bilgisayar Mühendisliği

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